1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure for testing the semiconductor device.
2. Description of the Background Art
For ensuring the reliability of products, various tests are performed on semiconductor devices. The tests of semiconductor device include a test at a wafer level and a test on a packaged device prior to shipment. For operations in various kinds of test modes, the semiconductor device is provided with circuit elements corresponding to the respective test modes. These circuit elements are selectively set to appropriate states in accordance with a designated test mode so that short-circuiting between internal nodes, change of an operation mode and others are performed. The test at the wafer level specifically includes a test for determining whether an internally produced reference voltage is set at a predetermined voltage level or not, and a performance evaluating test for determining whether internal circuits of the semiconductor device satisfy predetermined operation characteristics or not. Final tests after packaging specifically includes a screening test (voltage stress accelerated test) for revealing a latent defect.
The types of tests made on the semiconductor device increase with increase in integration density and number of functions of the semiconductor device. Increase in number of the types of test modes results in increase in number of corresponding circuit elements and therefore increase in area of the chip occupied by the circuit elements dedicated to the test operations so that the chip area increases, and the cost increases.
Various test modes are designated by combinations of states of a plurality of signals (e.g., WCBR+super VIH+address key). In this case, a designated test mode must be accurately determined, and the device must be set to the state corresponding to the designated test mode. If the device is set to an erroneous test mode state, an intended test could not be performed and the performance evaluation of the semiconductor device could not be made accurately.
Voltage acceleration is performed for accelerated tests such as a life test or a screening test of the product. In the case of the voltage acceleration, the voltage acceleration must be performed efficiently for reducing a test time. For example, if an internal power supply voltage is changed in accordance with an external power supply voltage in a semiconductor memory device, an internal voltage higher than the internal power supply voltage also rises. Therefore, the internal power supply voltage can be raised only to a restricted level because break down voltage must be ensured in portions receiving the internal voltage. This results in a problem that voltage acceleration on all the internal nodes cannot be performed efficiently.
Further, screening must be effected on various portions by voltage acceleration for ensuring the reliability.
An object of the invention is to provide a semiconductor device which allows accurate execution of intended tests without increase in chip area.
Another object of the invention is to provide a semiconductor device including a test circuit with a high circuit utilizing efficiency.
A further object of the invention is to provide a semiconductor device allowing accurate setting of intended test modes.
Still another object of the invention is to provide a semiconductor device in which voltage stress acceleration can be efficiently performed on an intended node.
According to the invention, a semiconductor device includes a circuit for generating first and second internal test mode instructing signals in response to an externally applied test mode instructing signal; a circuit for taking in an externally applied address signal and generating a test address signal in response to the first internal test mode instructing signal; and a test mode activating circuit for operating in accordance with the second internal test mode instructing signal and the test address signal to generate a test mode select signal for activating a test mode designated by the test address signal among a plurality of test modes.
The test address signal generating circuit includes a circuit for initializing the test address signal to a state different from the state for selecting one of the plurality of test modes.
By initializing the test address signal to the state different from the test mode instructing state, an intended test mode can be accurately activated even if the plurality of signals are varied in timing.
Further, by utilizing a tuning signal line in another test mode, the circuit utilizing efficiency is improved, and the area of the chip occupied by the test circuit is reduced.
By transmitting an internal voltage other than a sense power supply voltage to a sense power supply node of sense amplifiers, it is possible to perform voltage stress acceleration on each node of the sense amplifiers at a desired speed in a test operation mode.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.